1. Field of the Invention
The present invention relates to a method for the manufacture of semiconductor devices and more particularly to the method for forming a barrier layer in a damascene structure.
2. Description of the Prior Art
In the processes for the manufacture of semiconductor devices, when the active elements of these semiconductor devices are constructed, the following work will be the manufacture of the metal conductive layers above these active elements to complete the electrical interconnection inside the semiconductor devices. The processes for the manufacture of the metal conductive layers are usually as follows: first, forming a metal layer above the active regions of the semiconductor devices, second, proceeding with photoresist coating, developing, and etching to complete the manufacture of a first metal layer, third, depositing a dielectric layer on the first metal layer, and finally proceeding with the manufacture of multiple metal layers dependent on the needs of the different semiconductor devices.
For many years, materials of metal conductive layers of semiconductors are mainly aluminum and aluminum alloys. However, as sizes of semiconductor devices get more and more smaller, operating speeds of semiconductor devices get more and more faster, and power consumptions of semiconductor devices get more and more lower, it is necessary to use metal materials of lower resistivity and dielectric materials of low dielectric constant to complete the electrical interconnection inside semiconductor devices. U.S. Pat. No. 6,489,240 B1 cites using copper and dielectric materials of dielectric constant lower than 4 to complete the electrical interconnection inside semiconductor devices. When copper is used as the material of metal conductors of semiconductors, as shown in FIG. 1A, considering that copper is difficult to be vaporized after etching processes, a dual damascene structure 10 is often used to proceed with copper forming processes inside the dual damascene structure 10. U.S. Pat. No. 6,492,270 B1 mentions the details of forming copper dual damascene. A dual damascene structure 10 comprises a first etch-stop layer 120, a first dielectric layer 160, a second etch-stop layer 140, and a second dielectric layer 180. Before copper processes inside the dual damascene structure 10 above the copper metal layer 100 are performed, as shown in FIG. 1B, a barrier layer 190 has to be formed to prevent copper atoms from diffusing into surrounding dielectric layers.
In order to prevent copper atoms from diffusing into dielectric layers in the prior art, titanium nitride (TiN) or tantalum nitride (TaN) is usually used to form a barrier layer. U.S. Pat. No. 6,541,374 B1 mentions details of forming a barrier layer with TiN. Practically, when the barrier layer 190 is deposited, as a result of the direction of depositing is about perpendicular to the wafer surface, the thickness of the sidewall of the dual damascene structure 10 will be about one-fifth to a half of the thickness above the via bottom in the first dielectric layer 160 and above the trench bottom in the second dielectric layer 180, easily causing that the deposition of the sidewall of the dual damascene structure 10 is incomplete and copper atoms formed later in the dual damascene structure 10 diffuse into surrounding dielectric layers. Consequently the electric property of the surrounding dielectric layers will be affected and then the semiconductor devices will be damaged. Accordingly there is a need for completely depositing a barrier layer of the sidewall of a dual damascene structure 10 to prevent copper atoms from diffusing into surrounding dielectric layers.
In the other hand, the resistivity of nitrided metal materials in the prior art is far more higher than the resistivity of metal materials. Hence if TiN or TaN is used as the material of the barrier layer 190 in the dual damascene structure 10, the resistivity between metals in the dual damascene structure 10 will be so high that the operating speed and the power consumption of the semiconductor devices will be influenced. Therefore there is a need for reducing the resistivity of the barrier layer 190 above the via bottom in the first dielectric layer 160.